Semiconductor memory devices, such as, for example, dynamic random access memory (DRAM) store data in an array of cells with each cell storing one bit of data. The cell arrays are typically arranged in rows and columns such that a particular cell is addressed by specifying its row and column within the array. Cells in a row are connected together to a wordline and cells in a column are connected together to a bitline. Sense amplifiers connected to the detect data in the cells.
Each of DRAM cells includes a storage capacitor. As such, the cells are considered “dynamic”, since the stored data (i.e., charged capacitor) will dissipate after a relatively short period of time. In order to retain the stored data, the contents of the DRAM cells are refreshed on a periodic basis by reapplying the charged state of the storage capacitor of each cell in a repetitive manner. A refresh operation is similar to a read operation in that the data in the cells is sensed by the sense amplifiers and the data is rewritten to the cells. Thus, the data is “refreshed” in the cells. The refresh operation is performed by enabling a wordline according to a row address and enabling a sense amplifier. Refresh operations can be either “auto-refresh” performed when the DRAM is in an active mode or “self-refresh” performed when the DRAM is in a sleep mode.
A boost required for getting from an external supply voltage (Vdd) to a gate voltage of access transistor sufficient to charge the capacitors of the cells changes with various characteristics of the DRAM. For example, the amount of current boost required overcoming the voltage dropping when a refresh operation occurs in the sleep mode increases with decreasing refresh time. An internal voltage supply is typically configured without regard to variable refresh times, often relying on a consideration of only the worst possible refresh times. The refresh rate of the DRAM is typically set by the manufacturer to a time period that ensures that data will not be lost. However, this time period may be more frequent than necessary and it may be desirable to reduce this frequency in order to reduce power consumption. The maximum driving capacity of an internal voltage supply is typically determined according to the worst refresh characteristics (i.e., the shortest time period). It, thus, provides more current than is required and results in greater power consumption.
For example, DRAMs in the 0.13 μm to 0.18 μm size range typically have longer refresh time periods (e.g., over 8 ms) and as such the sleep mode current requirements are low. As the size of DRAMs decreases to around 90 nm, MIM (metal-insulator-metal) type capacitors having shorter and more variable refresh time periods are used. A self-refresh pump circuit may not easily handle this variability in the voltage boost and current to be produced. Therefore, the refresh time period may be set according to the shortest possible period. If the DRAM has a higher refresh time period, then it may result in over-pumping and inefficient power use in the sleep mode.